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April 1997
ML4642 AUI Multiplexer
GENERAL DESCRIPTION
The ML4642 AUI Multiplexer contains all the necessary drivers/receivers and control logic to implement a 2 port MAU when used in conjuction with a transceiver chip which has a standard 802.3 AUI interface. In addition, the ML4642 is capable of operating in stand-alone mode where it interconnects two DTEs in the absence of a network MAU. Several ML4642s can be cascaded together to implement a 4 or 8 port MAU or stand-alone device. Logic within the ML4642 detects collisions resulting from multiple DTEs transmitting simultaneously. In addition, collision signals received from a transceiver attached at the MAU port are propagated to both of the DTE ports. Jabbering DTEs are prevented from loading down the network by internal jabber timers which disable babbling ports. s
FEATURES
IEEE 802.3 compliant AUI interfaces assure compatibility with any AUI ready devices No crystal or clock input On-chip Jabber logic, Collision Detection, and SQE test with enable/disable option Selectable Loopback, Jabber, and SQE Test allows cascading of multiple chips to increase DTE port
s s
s
BLOCK DIAGRAM
+5V 61.9K RRSET
VCC
VCC
CONTROL LOGIC TXIN1P TXIN1N RXOUT1P RXOUT1N CDOUT1P CDOUT1N TXIN2P TXIN2N RXOUT2P RXOUT2N CDOUT2P CDOUT2N LED DRIVERS MAU AUI INTERFACE CI MUX MAU AUI INTERFACE JABBER
DO MUX DTE AUI INTERFACE
TXOUTP TXOUTN
DI MUX
RXINP RXINN CDINP CDINN
SQE SOURCE
GND
JAB1/JDIS
JAB2
CDLED
RXLED/LPBK/SQE
TXLED1
TXLED2
1
ML4642
PIN CONNECTIONS
ML4642 28-Pin SSOP (R28)
RXLED/LPBK/SQE RXINP RXINN JAB1/JDIS RRSET VCC TXOUTP TXOUTN TXLED1 TXLED2 TXIN2P TXIN2N TXIN1P TXIN1N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RXOUT1P RXOUT1N RXOUT2N RXOUT2P GND CDOUT1N CDOUT1P JAB2 CDINP CDINN CDLED CDOUT2P CDOUT2N VCC
TOP VIEW
ML4642 28-Pin PLCC (Q28)
RXLED/LPBK/SQE
RXOUT1N
27
4 RRSET VCC TXOUTP TXOUTN TXLED1 TXLED2 TXIN2P 5 6 7 8 9 10 11 12
3
2
1
28
26 25 24 23
RXOUT2N
RXOUT1P
JAB1/JDIS
RXINN
RXINP
RXOUT2P GND CDOUT1N CDOUT1P JAB2 CDINP CDINN
TOP VIEW
22 21 20 19 18
13 14
15
16
17
CDOUT2N
CDOUT2P
TXIN2N
TXIN1P
2
TXIN1N
CDLED
VCC
ML4642
PIN DESCRIPTIONS
PIN NO.
1
NAME
RXLED/LPBK/SQE
FUNCTION
I/O
DESCRIPTION Active low receive LED driver for MAU port. If tied to ground, this pin enables internal loopback of the active TXIN pair to the RXOUT pairs and enables SQE test. If tied to 0.6 volts internal loopback is enable but SQE test is disabled. SQE and loopback are disabled when this pin is pulled high. Receive signal pair for MAU port. Receive signal pair for MAU port. Active low jabber LED driver for DTE port 1. If tied to ground, the jabber function is disabled at TXIN1 and TXIN2. Bias setting external resistor, 61.9Ky. +5 volt power supply Transmit signal pair for MAU port. Transmit signal pair for MAU port. Open collector, active low transmit LED driver for DTE AUI port 1. Open collector, active low transmit LED driver for DTE AUI port 2. Transmit signal pair for DTE port 2. Transmit signal pair for DTE port 2. Transmit signal pair for DTE port 1. Transmit signal pair for DTE port 1. +5 volt power supply Collision signal pair for DTE port 2. Collision signal pair for DTE port 2. Open collector, active low collision LED driver. Collision signal pair for MAU port. Collision signal pair for MAU port. Open collector, active low jabber LED driver for DTE port 2. Collision signal pair for DTE port 1. Collision signal pair for DTE port 1. GND. Receive signal pair for DTE port 2. Receive signal pair for DTE port 2. Receive signal pair for DTE port 1. Receive signal pair for DTE port 1.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
RXINP RXINN JAB1/JDIS RRSET VCC TXOUTP TXOUTN TXLED1 TXLED2 TXIN2P TXIN2N TXIN1P TXIN1N VCC CDOUT2N CDOUT2P CDLED CDINN CDINP JAB2 CDOUT1P CDOUT1N GND RXOUT2P RXOUT2N RXOUT1N RXOUT1P
Input Onput I/O Input Power Output Output Output Output Input Input Input Input Power Output Output Output Input Input Output Output Output Ground Output Output Output Output
3
ML4642
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. Power Supply Voltage Range VCC . . . GND -0.3V to 6.0V Input Current RRSET, JAB1/JABD, JAB2, CDLED, RxLED/LPBK/SQE, TxLED1, TxLED2 . . . . . . . . . . 60mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . -65C to 150C Lead Temperature (Soldering 10 seconds) . . . . . . . 260C Thermal Resistance (qJA) SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109C/W PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68C/W
OPERATING CONDITIONS
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . 5V 10% LED on Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA RRSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.9ky 1%
ELECTRICAL CHARACTERISTICS
Unless otherwise specified TA = 0C to 70C, VCC = 5V 10%. (Notes 1, 2)
PARAMETER Power Supply Current ICC LED Drivers: VOL CONDITIONS VCC = 5V, (Note 3) RL=510y for CDLED, TXLED1,2, JAB2 RL=270y for JAB1/JDIS, RxLED/LPBK/SQE Transmit Squelch Voltage Level (Tx+, Tx-) Differential Output Voltage Common Mode Output Voltage Differential Output Voltage Imbalance RxLED/LPBK/SQE SQE Enabled/Loopback Enabled SQE Disabled/Loopback Enabled
Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. Note 2: Low Duty cycle pulse testing is performed at TA. Note 3: This does not include the current from the AUI pull down resistors or the LED output pins.
MIN
TYP. 60
MAX 120 0.8
UNITS mA V V mV mV V
1.2 -300 550
2.5 -250
3.5 -200 1200
4.0 2 40 0.3 0.4 0.6 0.8
mV V V
4
ML4642
AC ELECTRICAL CHARACTERISTICS
SYMBOLS TRANSMIT t TXNPW tTXFPW tXODY tTXLP tTXSDY tTXJ RECEIVE tRXODY tRXSDY tRXJ tAR tAF COLLISION tCPSQE tSQEXR tCLF t CLPDC tSQEDY tSQETD tSQEB Collision Present to SQE Assert Time for SQE to Deactivate after a collision Collision Frequency Collision Pulse Duty Cycle SQE Test Delay (Tx Inactive to SQE) SQE Test Duration SQE Blank Period 0 100 8.5 40 0.6 0.5 4 10 50 1.1 1.0 200 900 11.5 60 1.6 1.5 7 ns ns MHz % s s sec Receive Turn-On Delay Receive Steady State Prop. Delay Receiver Jitter Differential Output Rise Time 20% to 80% (Rx+/-, COL+/-) Differential Output Fall Time 20% to 80% (Rx+/-, COL+/-) 20 15 1 3 3 ns ns ns ns ns Transmit Turn-On Pulse Width Transmit Turn-Off Pulse Width Transmitter Turn-On Delay Transmit Loopback Startup Delay Transmit Steady State Prop. Delay Transmitter Jitter 20 180 30 40 15 1 ns ns ns ns ns ns PARAMETER MIN TYP. MAX UNITS
JABBER, LINK TEST AND LED TIMING tJAD tJRT tJSQE tLEDT Jabber Activation Delay Jabber Reset Unjab Time Delay from Outputs Disabled to Collision Oscillator On CDLED, RxLED, TxLED1, TxLED2 On Time 20 7 250 13.5 450 100 50 300 20 750 ms ms ns ms
5
ML4642
TIMING DIAGRAMS
tTXNPW TXINP TXINN VALID tTXODY TXOUTP TXOUTN tTXLP RXOUT1, 2, P RXOUT1, 2, N VALID DATA VALID DATA DATA tTXSDY tTXFPW
Figure 1. Transmit and Loopback Timing
RXINP RXINN VALID tRXODY RXOUT1, 2, P RXOUT1, 2, N VALID DATA DATA tRXSDY tAR tAF
Figure 2. Receive Timing
6
ML4642
TIMING DIAGRAMS (Continued)
TXIN2P TXIN2N VALID DATA
TXIN1P TXIN1N tCPSQE CDOUT1, 2, P CS0 CDOUT1, 2, N tTX2, TX1 TXOUTP TXIN2 TXOUTN TXIN2 TXIN2 TXIN1 TXIN1 TXIN1 VALID DATA
TXIN1P VALID TXIN1N DATA
TXIN2P VALID TXIN2N tCPSQE CDOUT1, 2, P CS0 CDOUT1, 2, N DATA
Figure 3. Collision Timing
TXIN1P TXIN1N
TXIN2P TXIN2N VALID tSQEXR CDOUT1, 2, P CDOUT1, 2, N CS0 DATA
TXOUTP TXOUTN TXIN1 TXIN1 TXIN2 TXIN2 TXIN2 TXIN2
Figure 4. Collision Timing
7
ML4642
TIMING DIAGRAMS (Continued)
TXIN2P TXIN2N
TXIN1P TXIN1N VALID tSQEXT CDOUT1, 2, P CDOUT1, 2, N CS0 DATA
TXOUTP TXOUTN TXIN1 TXIN1 TXIN1 TXIN1 TXIN1
1 tCLF
CDOUT1, 2, P CDOUT1, 2, N
Figure 5. Collision Timing
TXIN1P VALID DATA TXIN1N tSQETD tSQEDY tSQEB CDOUT1P CDOUT1N tSQEB CDOUT2P CDOUT2N (internal signal) CS0
Figure 6. SQE Timing
8
ML4642
TIMING DIAGRAMS (Continued)
TXIN1P VALID TXIN1N tJAD TXOUTP TXOUTN VALID DATA tJSQE CDOUT1P CS0 CDOUT1N tJRT DATA
Figure 7. Jabber Timing
TXOUT1P TXOUT1N tLEDT
TXLED1
RXINP RXINN tLEDT
RXLED
Figure 8. LED Timing
9
ML4642
FUNCTIONAL DESCRIPTION
Figure 9 is a block diagram of a Two Port Multiplexer using the ML4642 chip. All AUI interfaces are shown AC coupled as they would be in an AUI multiplexer which does not include the MAU circuitry on the same board. TRANSMISSION The transmit function consists of detecting data on either of the TXIN differential receivers (TXIN1 or TXIN2) and transmitting this data out the TXOUT differential driver at the MAU port as well as both RXOUT1 and RXOUT2 drivers of the DTE ports. (Note: the looping back of data received at a TXIN pair to the RXOUT pairs is discussed in the Loopback section.) Before data will be transmitted to the TXOUT and RXOUT pins from the TXIN pins it must meet the unsquelch requirements of the TXIN receiver circuitry. The squelch circuitry prevents any noise on the TXIN wires from being misinterpreted as data and transmitted to the TXOUT and RXOUT pins. The squelch circuit rejects signals with pulse widths less than typically 20ns and voltage levels more positive than -250mV. Once the TXIN receiver is unsquelched it remains so until reception of the input idle signal, which is detected when the TXIN signal is more positive than -170mV for longer than 180ns. RECEPTION The receive function consists of detecting data at the RXIN differential receiver of the MAU port transmitting this data to both DTE port RXOUT pairs.
+5V TXIN1P TXIN1N 39 39 VCC VCC GND 0.1 0.01 +5V 61.9K TXOUTP TXOUTN 360 CDOUT1P CDOUT1N 360 360 360
ML4642
RXOUT1P TO DTE 1 360 360 RXOUT1N
RRSET
RXINP RXINN 39 39 TO MAU
TXIN2P TXIN2N 39 39 CDINP CDINN 39 RXOUT2P TO DTE 2 360 360 RXOUT2N JAB1/JABD JAB2 CDLED CDOUT2P CDOUT2N 360 360 TXLED1 TXLED2 RXLED/LPBK/SQE 39
270 510 510 510 510 1 270 2 3 7.15k +5V
Switch Option 1. Receive LED with Internal/External MAU 2. No MAU/No SQE 3. No MAU with SQE
Q1
Q2
1k
1k
Figure 9. Two Port AUI Multiplexer
10
ML4642
FUNCTIONAL DESCRIPTION
Before data will be transmitted to the RXOUT pins of the DTE ports it must meet the unsquelch requirements for the RXIN receiver circuitry. The squelch circuitry at the RXIN differential receiver input performs the same function as that of the TXIN squelch circuitry using the same noise rejection criteria. COLLISION There are two conditions that constitute a collision from the point of view of the ML4642: a) If data is received at the TXIN inputs of both DTE ports simultaneously a local collision occurs within the ML4642. b) If the CDIN input is active at any time other than the inter-packet gap window allowed for the SQE Test function described below. In either of the above circumstances it is necessary for the ML4642 to drive the CDOUT pairs on both DTE ports with the collision signal. The collision signal consists of a 10 MHz +/- 15% square wave matching the AUI specifications and capable of driving a 78y load. The collision signal shall turn on within 2 bit times of the origination of the collision condition and shall turn off within 2-5 bit times after the collision condition subsides. During a collision condition there are two sources for data to be transmitted to TXOUT, TXIN1 and TXIN2. The highest priority source for data to be transmitted to TXOUT is the TXIN1 receiver. For example if TXIN2 begins transmission then TXIN1 turns on, the collision oscillator will turn on and TXOUT will switch from TXIN2 to TXIN1. If the collision ends by TXIN1 turning off first, TXOUT will switch from TXIN1 to TXIN2, and 2-5 bit times later the collision oscillator will turn off. The MAU port's CDIN receiver contains squelch circuitry to prevent noise from causing the erroneous detection of a collision signal. A signal on the CDIN pair will not be considered active until it exceeds the same squelch requirements as those of the TXIN receivers. LOOPBACK The loopback function allows the ML4642 to emulate a coaxial transceiver by propagating the TXIN data back out the RXOUT pair of the same DTE port that is sourcing the data as well as the RXOUT pair of the idle DTE port. This allows the Ethernet controller sending the data to monitor its transmit packets and detect network faults. The loopback function is enabled at both DTE ports when the RXLED pin is tied to ground, or 0.6 volts. SQE TEST FUNCTION The Signal Quality Error (SQE) Test function allows the DTE to determine whether or not the collision detection circuitry is functional. After each transmission, during the inter-packet gap time, the collision signal will be activated on the CDOUT pair of the same port as the TXIN pair which received the packet, for typically 1 s. The SQE function will not be activated on DTE ports of the ML4642 which are in the Jabber state. The SQE function is enabled on both DTE ports when the RXLED/ LPBK/SQE pin is grounded. JABBER The jabber function prevents a babbling transmitter from loading down the network. Within the ML4642 is a jabber timer on each TXIN receiver. Each timer starts at the beginning of a received packet and resets at the end of each packet. If a packet lasts longer than 7 to 20ms the jabber logic disables its corresponding TXIN receiver (thus preventing its data from being retransmitted) and generates a collision signal on the babbling port's CDOUT pair. When the TXIN pair finally goes idle, a second timer measures 0.5 seconds of idle on TXIN prior to re-enabling the receiver and turning off the collision signal. If the TXIN pair becomes active again before the 0.5 seconds has expired, the timer is reset and measures another 0.5 seconds of idle time. The jabber function can be disabled on both ports by tying the JAB1/JABD pin to ground. LED DRIVERS The ML4642 has six LED driver pins. Each DTE port has a transmit LED and a jabber LED and the MAU port has a receive LED. Additionally, there is a collision LED which indicates the presence of a collision condition. All LED drivers are active low 10mA current sources. The TXLED, RXLED, and CDLED outputs have 50ms pulse stretchers on them to enable the LEDs to be visible. The JLED outputs do not have pulse stretchers on them because their conditions occur long enough for the LEDs to be visible. Two of the ML4642 LED outputs serve as configuration pins as well. RXLED/LPBK/SQE and JAB1/JDIS may be tied through a resistor to VCC, tied through a resistor and a LED to VCC or grounded. Additionally RXLED/LPBK/SQE may be tied to a specific voltage. When these pins are grounded or tied to a 0.6 Volts they become configuration inputs. Otherwise when tied high they become status outputs. CASCADING THE ML4642 FOR 4 AND 8 PORT DESIGNS The configurability of such functions as loopback, jabber, and SQE allows ease of cascading multiple ML4642 chips for larger fan-out designs. Figure 10 shows a four port AUI Multiplexer design. For a type 0 configuration both jabber and transmit LEDs are available on a per port basis for status. The RXLED/LPBK/SQE pins are tied through a resistor to 5 volts, and CDLED is wire OR'ED with the other chip for one collision detect status LED per system. There is also only one receive LED status output which is displayed in a type 2 configuration. This particular pin in
11
ML4642
FUNCTIONAL DESCRIPTION
Type 0
+5V TXIN1P TXIN1N 39 39 VCC VCC GND 0.1 0.01 +5V 61.9K TXOUTP TXOUTN 1k CDOUT1P CDOUT1N 360 360 1k
ML4642
TO DTE 1 RXOUT1P RXOUT1N 360 360
RSSET
RXINP RXINN 1k 1k
TXIN2P TXIN2N 39 39 CDINP CDINN 1k TO DTE 2 RXOUT2P RXOUT2N 360 360 JAB1/JABD JAB2 CDLED CDOUT2P CDOUT2N 360 360 TXLED1 TXLED2 RXLED/LPBK/SQE 510 510 270 1k TXIN1P TXIN1N
Type 2
+5V VCC VCC GND 0.1 0.01 +5V 61.9k TXOUTP TXOUTN 360 CDOUT1P CDOUT1N 360
270 510
ML4642
RXOUT1P RXOUT1N
RSSET
RXINN 39 39
TXIN2P TXIN2N CDINP CDINN +5V TXIN1P TXIN1N 39 39 VCC VCC GND 0.1 0.01 +5V 61.9k CDOUT2P TXOUTP TXOUTN 1k CDOUT1P CDOUT1N 360 360 1k CDOUT2N RXOUT2P RXOUT2N JAB1/JABD JAB2 CDLED TXLED1 TXLED2 RXLED/LPBK/SQE NC NC NC NC 1 270 2 3 RXINP RXINN 1K 1K 1k CDINP CDINN 1K TO DTE 4 RXOUT2P RXOUT2N 360 360 JAB1/JABD JAB2 CDLED CDOUT2P CDOUT2N 360 360 TXLED1 TXLED2 RXLED/LPBK/SQE 510 510 270 +5V Switch Options 1. Receive LED with Internal/External MAU 2. No MAU/No SQE 3. No MAU with SQE 1K 1k Q1 Q2 7.15k +5V 39 39
ML4642
TO DTE 3 RXOUT1P RXOUT1N 360 360
RSSET
TXIN2P TXIN2N 39 39
270 510 510 +5V
Figure 10. Four Port AUI Multiplexer
12
TO MAU
+5V
RXINP
ML4642
FUNCTIONAL DESCRIPTION
a type 2 configuration offers three options. In option 1, when tied to +5 volts through a resistor and an LED, an internal or external MAU will be connected. For standalone operation without an internal or external MAU a loopback is required. Option 2 allows loopback with no SQE test while option 3 provides loopback with an SQE test. An eight port design is accomplished in the same way as shown in the block diagram in Figure 11. In an eight port design Type 0 and Type 2 configuration remain the same as in a four port design. Type 1 however only differs from Type 2 by tying RXLED/LPBK/SQE through a resistor to +5 volts. Table 1 summerizes all of the different LED configurations. SQE TEST WHEN CASCADING As mentioned before, after each transmission during the interpacket gap time the collision signal will be activated on the CDOUT pair of the same port as the TXIN pair which received the packet. When cascading ML4642s to implement 4 or 8 port designs, the path is remembered and followed to acheive this function. The paths that did not carry the transmit data blocks CDOUT for 4-7 sec after transmission to guarantee that only the port that transmitted will see SQE test.
TABLE 1. LED Configurations for 2, 4, and 8 Port Designs
JAB1/JABD Two Port AUI Mux Type 0 Type 1 Type 2 LED LED GND GND RXLED/LPBK/SQE GND, 0.6V, LED 270y to +5V 270y to +5V GND, 0.6V, LED JAB2 LED LED NC NC CDLED LED WIRE'ORED NC NC TXLED1 LED LED NC NC TXLED2 LED LED NC NC
TYPE 0
TYPE 1
TYPE 2
DTE PORT 1 ML4642 DTE PORT 2 ML4642 DTE PORT 3 ML4642 DTE PORT 4 ML4642 DTE PORT 5 ML4642 DTE PORT 6 ML4642 DTE PORT 7 ML4642 DTE PORT 8 MAU PORT
Figure 11. Eight Port AUI Multiplexer
13
ML4642
PHYSICAL DIMENSIONS inches (millimeters)
Package: R28 28-Pin SSOP
0.397 - 0.407 (10.08 - 10.34) 28
0.205 - 0.213 (5.20 - 5.40) PIN 1 ID
0.301 - 0.313 (7.65 - 7.95)
1 0.026 BSC (0.65 BSC) 0.068 - 0.078 (1.73 - 1.98) 0 - 8
0.066 - 0.070 (1.68 - 1.78)
0.009 - 0.015 (0.23 - 0.38)
SEATING PLANE
0.002 - 0.008 (0.05 - 0.20)
0.022 - 0.030 (0.55 - 0.95)
0.004 - 0.008 (0.10 - 0.20)
Package: Q28 28-Pin PLCC
0.485 - 0.495 (12.32 - 12.57) 0.450 - 0.456 (11.43 - 11.58) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22)
PIN 1 ID 8 22 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.300 BSC (7.62 BSC) 0.390 - 0.430 (9.90 - 10.92)
15 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28)
0.099 - 0.110 (2.51 - 2.79)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
14
ML4642
ORDERING INFORMATION
PART NUMBER ML4642CR ML4642CQ TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 28-Pin SSOP (R28) 28-Pin PLCC (Q28)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4642-01
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